Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques

Agfianto Eko Putra; Oskar Natan; Jazi Eko Istiyanto

doi:10.31436/iiumej.v26i1.3328

Authors

Agfianto Eko Putra Universitas Gadjah Mada https://orcid.org/0000-0002-1568-6864
Oskar Natan Universitas Gadjah Mada https://orcid.org/0000-0003-3896-0448
Jazi Eko Istiyanto Universitas Gadjah Mada https://orcid.org/0009-0000-5670-6481

DOI:

https://doi.org/10.31436/iiumej.v26i1.3328

Keywords:

sha-3, FPGA, dsp48, pipeline

Abstract

Deploying SHA-3 on FPGA devices requires significant resource allocation; however, the resulting throughput still needs improvement. This study employs the DSP48 module on the Xilinx FPGA to address this issue and implements an eight-stage pipeline methodology to minimize latency. The implementation design comprises a datapath and controller module, utilizing a Xilinx Artix-7-100T series FPGA as the hardware. This method makes use of FPGA resources like Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), and Buffer (BUFG). The system's highest frequency is 107.979 MHz, achieving different throughputs for cryptographic hash functions. Specifically, it performs a throughput of 5.183 Gbps for SHA3-224, 4.895 Gbps for SHA3-256, 3.743 Gbps for SHA3-384, and 2.591 Gbps for SHA3-512.

ABSTRAK: Menggunakan SHA-3 pada peranti FPGA memerlukan peruntukan sumber yang ketara, walaupun daya pengeluaran yang terhasil adalah terhad. Untuk menangani isu ini, kajian ini menggunakan modul DSP48 yang disertakan pada Xilinx FPGA dan melaksanakan metodologi saluran paip lapan peringkat untuk meminimumkan kependaman. Reka bentuk pelaksanaan terdiri daripada laluan data dan modul pengawal, menggunakan siri FPGA Xilinx Artix-7-100T sebagai perkakasan. Kaedah ini menggunakan sumber FPGA seperti Look-Up Tables (LUT), Look-Up Table Random Access Memory (LUTRAM), Flip-Flops (FF), Block RAM (BRAM), Digital Signal Processing (DSP), Input/Output (IO), dan Penampan (BUFG). Kekerapan tertinggi sistem ialah 107.979 MHz, dan ia mencapai daya pemprosesan yang berbeza untuk fungsi cincang kriptografi yang berbeza. Secara khususnya, ia mencapai daya pemprosesan 5.183 Gbps untuk SHA3-224, 4.895 Gbps untuk SHA3-256, 3.743 Gbps untuk SHA3-384 dan 2.591 Gbps untuk SHA3-512.

Downloads

Download data is not yet available.

Metrics

Metrics Loading ...

References

Paar, C. dan Pelzl, J., 2010, "SHA-3 and The Hash Function Keccak", Understanding Cryptography — A Textbook for Students and Practitioners, Available: http://www.crypto-textbook.com/. DOI: https://doi.org/10.1007/978-3-642-04101-3

Honda, T., Guntur, H. dan Satoh, A., 2014, "FPGA implementation of new standard hash function Keccak," 2014 IEEE 3rd Global Conference on Consumer Electronics, GCCE 2014, Available: DOI:10.1109/GCCE.2014.7031105. DOI: https://doi.org/10.1109/GCCE.2014.7031105

Ahmad, I, and Das, A.S., 2005, Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs, Computers and Electrical Engineering 31 (2005) 345–360. DOI: https://doi.org/10.1016/j.compeleceng.2005.07.001

Rao, M., Newe, T. dan Grout, I., 2014, "Efficient high-speed implementation of secure hash algorithm-3 on Virtex-5 FPGA", Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014, Available: DOI:10.1109/DSD.2014.24. DOI: https://doi.org/10.1109/DSD.2014.24

Sideris, A.; Dasygenis, M., 2023, Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA. Computation 2023, 11, 152. https://doi.org/10.3390/computation11080152. DOI: https://doi.org/10.3390/computation11080152

Augoestien, N.G. dan Putra, A.E., 2015, “Purwarupa Perangkat Keras untuk Eksekusi Algoritma AES Berbasis FPGA”, IJEIS (Indonesian Journal of Electronics and Instrumentation Systems), [Online] Available: DOI:10.22146/ijeis.7644. DOI: https://doi.org/10.22146/ijeis.7644

M. Psarakis, A. Dounis, A. Almabrok, S. Stavrinidis, and G. Gkekas, "An FPGA-Based Accelerated Optimization Algorithm for Real-Time Applications," Journal of Signal Processing Systems, vol. 92, no. 10, pp. 1155-1176, Oct. 2020. doi: 10.1007/s11265-020-01522-5. DOI: https://doi.org/10.1007/s11265-020-01522-5

Kundi, D. e. S. dan Aziz, A., 2016, "A low-power SHA-3 designs using embedded digital signal processing slice on FPGA", Computers and Electrical Engineering, Available: DOI:10.1016/j.compeleceng.2016.04.004. DOI: https://doi.org/10.1016/j.compeleceng.2016.04.004

W. Wang and G. Sun, "A DSP48-Based Reconfigurable 2-D Convolver on FPGA," 2019 International Conference on Virtual Reality and Intelligent Systems (ICVRIS), Jishou, China, 2019, pp. 342-345. doi: 10.1109/ICVRIS.2019.00089. DOI: https://doi.org/10.1109/ICVRIS.2019.00089

E. Walters, "Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs," Computers, vol. 5, no. 4, p. 20, Sep. 2016. doi: 10.3390/computers5040020. DOI: https://doi.org/10.3390/computers5040020

I. M. Alexandru, A. Grama, L. Viman, and D. Pitica, "FFT Radix2 Core Implemented on FPGA with DSP48 Slices," 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME), Iasi, 2018, pp. 109-113. doi: 10.1109/SIITME.2018.8599234. DOI: https://doi.org/10.1109/SIITME.2018.8599234

A. Sideris, T. Sanida, and M. Dasygenis, "Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA," Journal of Cryptographic Engineering, vol. 14, no. 2, pp. 193-205, Jun. 2024. doi: 10.1007/s13389-023-00334-0. DOI: https://doi.org/10.1007/s13389-023-00334-0

Z. Han, J. Jiang, J. Xu, P. Zhang, X. Zhao, D. Wen, and Y. Dou, "A high-throughput scalable BNN accelerator with fully pipelined architecture," CCF Transactions on High Performance Computing, vol. 3, no. 1, pp. 17-30, Mar. 2021. doi: 10.1007/s42514-020-00059-0. DOI: https://doi.org/10.1007/s42514-020-00059-0

Sundal, M. dan Chaves, R., 2017, "Efficient FPGA Implementation of the SHA-3 Hash Function", Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, [Online] Available: DOI:10.1109/ISVLSI.2017.24. DOI: https://doi.org/10.1109/ISVLSI.2017.24

CENTER, CSR, 2021, "Cryptographic Standards and Guidelines," Available: https://csrc.nist.gov/projects/cryptographic-standards-and-guidelines/example-values,

Xilinx, 2020, "UltraFast Design Methodology Guide for the Vivado Design Suite," Xilinx, Available: https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2020_1/ug949-vivado-design-methodology.pdf.

Athanasiou, G.S., Makkas, G.P. dan Theodoridis, G., 2014, "High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm", ISCCSP 2014 - 2014 6th International Symposium on Communications, Control and Signal Processing, Proceedings, Available: DOI:10.1109/ISCCSP.2014.6877931. DOI: https://doi.org/10.1109/ISCCSP.2014.6877931

A. E. Putra, O. Natan, and J. E. Istiyanto, “Enhancing CNN Deployment Efficiency on Mobile Devices with FPGA-based Accelerators: Memory-based Convolution and Resource Optimization,” ICIC Express Letters Part B: Applications, vol. 15, no. 10, pp. 989-997, Oct. 2024.

Xilinx Inc., 2020, "Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide", Xilinx,. Available: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug953-vivado-7series-libraries.pdf.

Z. Hakim, O. Natan, R. H. Sari, J. T. Amael, A. Dharmawan and J. E. Istiyanto, "6-DOF Arm Robot Control Using Open-Source FPGA," 2024 9th International Conference on Control and Robotics Engineering (ICCRE), Osaka, Japan, 2024, pp. 157-161 DOI: https://doi.org/10.1109/ICCRE61448.2024.10589887

F. Kahri, B. Bouallegue, M. Machhout, R. Tourki, “An FPGA Implementation and Comparison of the SHA-256 and Blake-256”, 14th international conference on Sciences and Techniques of Automatic control, & computer engineering, Sousse, Tunisia 2013, pp 152-157. DOI: https://doi.org/10.1109/STA.2013.6783122

B. Jungk, "Evaluation Of Compact FPGA Implementations For All SHA-3 Finalists", Third SHA-3 Candidate Conference, March, 2012. DOI: https://doi.org/10.1109/ReConFig.2011.16

I. San, N. At, “Compact Keccak Hardware Architecture for Data Integrity and Authentication on FPGAs”, Information Security Journal: A Global Perspective, Taylor & Francis, 21:5, 231-242, 2012. DOI: https://doi.org/10.1080/19393555.2012.660678

J.-P. Kaps, P. Yalla, K.K. Surapathi, B. Habib, S. Vadlamudi, S. Gurung, “Lightweight Implementations of SHA-3 Finalists on FPGAs”, SHA-3 Conference, March 2012. DOI: https://doi.org/10.1007/978-3-642-25578-6_20