A Technique for Designing Variation Resilient Subthreshold Sram Cell

Authors

  • Aminul Islam Birla Institute of Technology (deemed university)

DOI:

https://doi.org/10.31436/iiumej.v14i1.318

Abstract

This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is similar to the standard read-decoupled 8-transistor (RD8T) SRAM cell with the exception that the access FETS are replaced with transmission gates (TGs). In this work, various design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time) and TWA (write access time) respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35×) and TWA distribution (3.79×) compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD) and 1.64× lower bitline leakage current (ILEAK) respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58×) tighter spread in IREAD (ILEAK) compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency @ 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.

 

ABSTRAK: Kertas kerja ini membentangkan teknik merekabentuk sel bawah ambang SRAM yang bolehubah. Senibina sel yang dicadangkan adalah sama dengan sel SRAM 8-transistor (RD8T) “pisahan-bacaan” piawai kecuali FET akses  digantikan dengan sel pintu transmisi (TGs). Di dalam kajian ini, beberapa metrik rekabentuk dinilai dan dibandingkan dengan sel RD8T SRAM. Rekabentuk yang dicadangkan menawarkan  peningkatan 2.14× dan 1.75×  dalam TRA (masa akses baca) dan TWA (masa akses tulis) berbanding dengan RD8T. Ia membuktikan kekukuhan variasi proses dengan menampilkan tebaran yang lebih sempit dalam pengagihan TRA (2.35 ×) dan pengagihan TWA (3.79 ×) berbanding dengan RD8T. Sel-Bit yang dicadangkan mempunyai arus baca 1.16 × lebih tinggi  (IREAD) dan arus bocor bitline 1.64 × lebih rendah (ILEAK) berbanding dengan RD8T. Ia juga membuktikan kekukuhan dengan menawarkan 1.34 × (1.58 ×) penyebaran sempit di IREAD (ILEAK) berbanding dengan RD8T dan nisbah IREAD / ILEAK 1.42 × lebih besar. Ia menunjukkan kekerapan 2.2 × lebih tinggi pada 250 mV dengan kemuatan membaca bitline sebanyak 10 fF. Selain itu, sel bit yang dicadangkan mencapai kestabilan membaca dan keupayaan menulis yang sama seperti RD8T dengan kos tambahan 3 transistor. Kebocoran kuasa  rekabentuk yang dicadangkan hampir sama dengan RD8T.


KEYWORDS: variability; robust, subthreshold; random dopant fluctuation (RDF); read static noise margin (RSNM); write static noise margin (WSNM).

Downloads

Download data is not yet available.

Author Biography

Aminul Islam, Birla Institute of Technology (deemed university)

Aminul Islam (M’10) graduated in Computer Engineering from The Institution of Engineers (India) in 2001, and post graduated in Electronics and Communication Engineering from Birla Institute of Technology (deemed university), Mesra, Ranchi, Jharkhand, India in 2006. Until November 2006, he was with Indian Air Force. Since November 2006, he has been with the Electronics and Communication Engineering Department, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India, where he is currently an Asst. Professor.

His research interests include VLSI/CAD design for classical CMOS, non-classical CMOS and non-CMOS (non-Silicon) technologies [which centre around the emerging technologies like FinFET, CNFET (Carbon Nanotube Field Effect Transistor), NWFET (Nanowire FET), TFET (Tunnel FET), GNFET (Graphene Nanoribbon FET) and Spintronics (Spin Transistor)], robust design of ultra-low power nanoscale circuit for portable computing and wireless communications. He has completed and submitted his Ph.D. research work in the field of VLSI design from the Department of Electronics Engineering, Aligarh Muslim University, Aligarh, (U.P.), India. He is the author or coauthor of more than 35 research papers in reputed journals and conference proceedings.

Downloads

Published

2013-03-04

How to Cite

Islam, A. (2013). A Technique for Designing Variation Resilient Subthreshold Sram Cell. IIUM Engineering Journal, 14(1). https://doi.org/10.31436/iiumej.v14i1.318

Issue

Section

Articles