• Aminul Islam Birla Institute of Technology (Deemed University)
  • Mohd. Hasan Aligarh Muslim University



This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).


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Author Biographies

Aminul Islam, Birla Institute of Technology (Deemed University)

Aminul Islam (M’10) graduated in Computer Engineering from The Institution of Engineers (India) in 2001, and post graduated in Electronics and Communication Engineering from Birla Institute of Technology (deemed university), Mesra, Ranchi, Jharkhand, India in 2006. Until November 2006, he was with Indian Air Force. Since November 2006, he has been with the Electronics and Communication Engineering Department, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India, where he is currently an Asst. Professor.

His research interests include Very Large Scale Integrated (VLSI) design/computer-aided design for nanoscale Silicon and non-Silicon technologies [that includes FinFET, Carbon Nanotube Field Effect Transistor (CNFET), Nanowire], robust design of ultra-low power nanoscale circuit for portable computing and wireless communications, VLSI testing, reconfigurable computing, and emerging technologies.  He is currently working toward the Ph.D. degree in the field of VLSI design from the Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, India. He has published more than 16 research papers in reputed Conferences and Journals.

Mohd. Hasan, Aligarh Muslim University

Dr. Mohd Hasan received the B.Tech. degree in Electronics Engineering from Aligarh Muslim University (AMU), India in 1990, the M.Tech. degree in Integrated Electronics and Circuits from the IIT, Delhi, India in 1992 and joined as Lecturer in Electronics Engineering Department of AMU in 1992. He received the Ph.D. degree from the University of Edinburgh, UK in 2004 on a Commonwealth Scholarship in the area of Low Power Architectures for Multi-carrier Systems. He has also worked as a postdoctoral visiting researcher on a prestigious Royal Academy of Engineering, UK funded project on Low Power FPGA Architecture in 2008-2009 in the School of Engineering, University of Edinburgh, UK. He has been currently working as Professor at Aligarh Muslim University, Aligarh, India since 2005. He has published seventy nine research papers in reputed Journals and Conferences. His research interest includes Low power VLSI design, Nanoelectronics, FPGA Architectures along with Embedded System Design.



How to Cite

Islam, A., & Hasan, M. (2011). VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY. IIUM Engineering Journal, 12(1), 13–30.