ADVANCING SYSTEM INTEGRATION: VERILOG-BASED HARDWARE IMPLEMENTATION OF AN ASIC INTERFACE FOR THREE AMBA PROCESSORS
DOI:
https://doi.org/10.31436/iiumej.v25i1.2914Keywords:
Nitinol, Silicon, Shape memory alloy, powder metallurgyAbstract
This paper presents the development of a multi-AMBA system processor interface employing multiple AMBA processors. The primary goal of this interface is to establish connections between various AMBA AHB interfaces and external memory units such as RAM and REGISTER, leveraging the high-performance capabilities of AMBA AHB. The research delves into the utilization of ASICs to integrate processors and functional blocks into a System-On-Chip (SoC) configuration, enabling the execution of intricate applications. Within the ASIC environment, the research explores how processors communicate with their designated targets through an interface that standardizes the communication protocol for all targets. It underscores the challenges posed by data throughput and inter-processor/RTL communication in contemporary processors and suggests the concurrent use of multiple AMBA processors for accessing their respective targets. Additionally, the paper introduces an arbitration system for managing multiprocessor access and investigates the optimization of bulk data access while prioritizing crucial ASIC design constraints, including speed, low power consumption, and efficient area utilization. The proposed system was rigorously validated through simulation using Verilog HDL, yielding positive and promising results.
ABSTRAK: Kajian ini adalah mengenai pembangunan antara muka, sistem pemproses berbilang AMBA yang mengandungi berbilang pemproses AMBA. Tujuan antara muka ini adalah bagi mewujudkan hubungan pelbagai antara muka AMBA AHB dengan unit memori luaran seperti RAM dan REGISTER, ini sekaligus memanfaatkan keupayaan tinggi AMBA AHB. Kajian ini mengguna pakai ASIC bagi menyatukan pemproses dan blok berfungsi pada konfigurasi Sistem-Atas-Cip (SoC), membolehkan pelaksanaan aplikasi rumit. Pada persekitaran ASIC, kajian ini meneroka cara pemproses berkomunikasi dengan sasaran yang ditetapkan melalui perantaraan antara muka yang menyeragam protokol komunikasi bagi semua sasaran. Ia menggariskan cabaran yang ditimbulkan oleh pemprosesan data dan komunikasi antara pemproses/RTL dalam pemproses kontemporari dan mencadang penggunaan secara serentak pemproses berbilang AMBA bagi mengakses sasaran masing-masing. Selain itu, kertas kerja ini memperkenalkan sistem timbang tara bagi mengurus akses berbilang pemproses dan mengkaji akses data pukal yang optimum sambil mengutamakan kekangan reka bentuk ASIC, seperti kelajuan, penggunaan kuasa rendah dan penggunaan kawasan secara cekap. Sistem ini telah disahkan dengan teliti melalui simulasi menggunakan Verilog HDL, memberikan dapatan positif dan harapan baik.
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