A New VLSI Architecture for High-Performance Parallel Turbo Decoder

sujatha elukuru; SUBHAS CHENNAPALLI; GIRIPRASAD  MAHENDRA NANJAPPA

doi:10.31436/iiumej.v23i2.2272

Authors

Sujatha Elukuru SreeVidyanikethan Engineering College https://orcid.org/0000-0002-7007-8888
Subhas Chennapalli
Giriprasad Mahendra Nanjappa

DOI:

https://doi.org/10.31436/iiumej.v23i2.2272

Keywords:

Turbo decoder, MAP decoder, VLSI, Interleaver, FPGA

Abstract

Recent wireless communications demand maximum achievable data rates without intervention. The channel decoder in the physical layer would support such high data rates with a flexible hardware structure. The turbo channel decoder offers flexible hardware architecture and reliable decoding, but the turbo decoder design is complex and its hardware architecture consumes more power and area in a communication system. Hence, an optimized high-performance turbo decoder architecture with simplified QPP interleaver is needed for supporting various data rates. In this context, this article presents a new hardware architecture with a three-stage pipeline parallel turbo decoding process and each MAP decoder in the proposed parallel turbo decoder with a three-stage micro pipeline processing is presented. The proposed structure optimized the circuit complexity and improved the throughput through parallel pipeline decoding. Also, this article presents a simplified semi-recursive QPP interleaver, which avoids complex ‘mod‘ operations for a high-performance turbo decoder. The performance analysis has been done using Model sim, Xilinx Vivado design suite, and estimated performance analysis was observed on various 28 nm CMOS technology FPGAs and compared with the conventional designs. Analysis of the proposed design showed improvement in throughput up to 55.6% and a reduction in the power consumption up to 43% as compared to the recently reported architectures.

ABSTRAK: Komunikasi tanpa wayar terkini menuntut kadar data maksimum yang boleh dicapai tanpa intervensi. Penyahkod saluran dalam lapisan fizikal akan menyokong kadar data yang tinggi dengan struktur perkakasan fleksibel. Penyahkod saluran turbo menawarkan seni bina perkakasan fleksibel dan penyahkodan yang boleh dipercayai. Tetapi, penyahkod turbo merupakan blok yang kompleks, lebih berkuasa dan menggunakan kawasan yang luas dalam sistem komunikasi. Oleh itu, seni bina penyahkod turbo optimum berprestasi tinggi dengan antara lembar QPP yang mudah diperlukan bagi menyokong pelbagai kadar data. Dalam konteks ini, kajian ini merupakan seni bina perkakas baru dengan proses penyahkod turbo selari bersama salur paip tiga peringkat dan setiap penyahkod MAP yang dicadangkan dalam penyahkod turbo selari bersama proses saluran paip mikro tiga peringkat dibentangkan. Struktur yang dicadangkan dapat mengurangkan kerumitan litar dan meningkatkan daya pemprosesan melalui penyahkodan saluran paip selari. Selain itu, kajian ini merupakan antara lembar mudah QPP rekursif, yang dapat mengelakkan operasi 'mod' yang kompleks bagi penyahkod turbo berprestasi tinggi. Analisis prestasi telah dilakukan menggunakan sim Model, reka bentuk suit Xilinx Vivado, dan analisis prestasi anggaran telah diperhatikan pada pelbagai teknologi FPGA CMOS 28 nm dan dibandingkan dengan reka bentuk konvensional. Analisis reka bentuk yang dicadangkan menunjukkan peningkatan sepanjang 55.6% dan pengurangan penggunaan kuasa sehingga 43% berbanding seni bina laporan terkini.

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Author Biographies

Subhas Chennapalli

Professor, Department of Electronics and Communications, JNTU College of Engineering, Andhra Pradesh, India

Giriprasad Mahendra Nanjappa

Professor, Department of Electronics and Communications, JNTU College of Engineering, Andhra Pradesh, India

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