Analytical Model of Subthreshold Swing for Junctionless Double Gate MOSFET Using Ferroelectric Negative Capacitance Effect
DOI:
https://doi.org/10.31436/iiumej.v24i1.2508Keywords:
Subthreshold swing, Junctionless, Ferroelectric, Negative capacitance, Double gateAbstract
An analytical Subthreshold Swing (SS) model is presented to observe the change in the SS when a stacked SiO2-metal-ferroelectric structure is used as the oxide film of a JunctionLess Double Gate (JLDG) MOSFET. The SS of 60 mV/dec or less is essential to reduce power dissipation while maintaining transistor performance. If a ferroelectric material with Negative Capacitance (NC) effect is used, the SS can be reduced below 60 mV/dec. The analytical SS model of the ferroelectric NC FET presented to analyze this was in good agreement with the SS derived from the relation between the drain current and gate voltage, using 2D potential distribution. As results were derived from the analytical SS model, it was found that it is possible to obtain an SS of 60 mV/dec or less even at 15 nm channel length by adjusting the thicknesses of the silicon channel, SiO2, and ferroelectric. In particular, the change in SS according to the ferroelectric thickness was saturated as the thickness of SiO2 increased and was almost constant as the thickness of the silicon channel decreased.
ABSTRAK: Model Ayunan Subambang (SS) analitikal dibentangkan bagi melihat perubahan pada SS apabila struktur feroelektrik-logam-SiO2 bertindan digunakan sebagai filem oksida bagi MOSFET Dua Get Tanpa Simpang (JLDG). SS 60 mV/dec atau kurang adalah penting bagi mengurangkan pelesapan kuasa sambil mengekalkan prestasi transistor. Jika bahan feroelektrik dengan kesan Kapasitans Negatif (NC) digunakan, SS dapat dikurangkan bawah 60 mV/dek. Model SS analitikal feroelektrik NC FET yang digunakan bagi kajian ini adalah sesuai dengan SS yang diperoleh daripada hubungan antara arus serapan dan voltan get, menggunakan edaran potensi 2D. Dapatan terbitan melalui model SS analitikal, mendapati bahawa adalah mungkin bagi mendapatkan SS pada 60 mV/dek atau kurang walaupun panjang laluan adalah 15 nm dengan melaraskan ketebalan saluran silikon, SiO2, dan feroelektrik. Terutama apabila perubahan ketebalan feroelektrik SS adalah tepu ketika ketebalan SiO2 meningkat, dan hampir malar apabila ketebalan saluran silikon berkurang.
Downloads
Metrics
References
RK Cavin RK, Lugli P, Zhirnov VV. (2012) Science and Engineering Beyond Moore’s Law. Proc. IEEE, 100: 1720-1749. doi:10.1109/JPROC.2012.2190155 DOI: https://doi.org/10.1109/JPROC.2012.2190155
Mack CA. (2011) Fifty Years of Moore’s Law. IEEE Trans. Semiconductor Manufacturing, 24(2): 202-207. doi:10.1109/TSM.2010.2096437 DOI: https://doi.org/10.1109/TSM.2010.2096437
Waldrop MM. (2016) The chips are down for Moore’s law. Nature News, 530: 144-147. DOI: https://doi.org/10.1038/530144a
Taur Y, Ning TH. (2020) Fundamentals of Modern VLSi Devices. Cambridge University Press, 2nd Edn. DOI: https://doi.org/10.1017/9781108847087
Nadeem M, Bernardo ID, Wang X, Fuhrer MS, Culcer D. (2021) Overcoming Boltzmann’s Tyranny in a Transistor vis the Topological Quantum Field Effect. Nano Lett. 21(7): 3155-3161. doi:10.1021/acs.nanolett.1c00378 DOI: https://doi.org/10.1021/acs.nanolett.1c00378
Hoffmann M, Slesazeck S, Mikolajick T. (2021) Progress and future prospects of negative capacitance electronics: A materials perspective. APL Materials, 9: 020902. doi:10.1063/5. 0032954 DOI: https://doi.org/10.1063/5.0032954
Iniguez J, Zubko P, Lukyanchuk I, Cano A. (2019) Ferroelectric negative capacitance. Nature Reviews Materials, 4: 243-256. doi:10.1038/s41578-019-0089-0 DOI: https://doi.org/10.1038/s41578-019-0089-0
Saha AK, Gupta SK. (2021) Negative capacitance effects in ferroelectric heterostructures: A theoretical perspective. J. Appl. Phys., 129: 080901. doi:10.1063/5.0038971 DOI: https://doi.org/10.1063/5.0038971
Hoffmann M, Gui M, Slesazeck S, Fontanini R, Segatto M, Esseni D, Mikolajick T. (2022) Intrinsic Nature of Negative Capacitance in Multidomain Hf0.5Zr0.5O2-Based Ferroelectric/ Dielectric Heterostructures. Advanced Functional Materials, 32: 2108494. DOI: https://doi.org/10.1002/adfm.202108494
doi:10.1002/adfm. 202108494
Hoffmann M, Fengler FPG, Max B, Schroeder U, Slesazeck S, Mikolajick T. (2019) Negative Capacitance for Electrostatic Supercapacitors. Advaced Energy Materials, 9: 1901154. DOI: https://doi.org/10.1002/aenm.201901154
doi:10. 1002/aenm.201901154
Zhang S, Lui H, Zhou J, Liu Y. (2021) ZrOx Negative Capacitance Field-Effect Transistor with Sub-60 Subthreshold Swing Behavior. Nanoscale Research Letters, 16: 21.
doi:10.1186/s11671-020-03468-w DOI: https://doi.org/10.1186/s11671-020-03468-w
Deepa R, Devi MP, Vignesh NA, Kanithan S. (2022) Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET. Silicon, 14: 2409-2419. doi:10.1007/s12633-022-01722-7 DOI: https://doi.org/10.1007/s12633-022-01722-7
Cao W, Banerjee K. (2020) Is negative capacitance FET a steep-slope logic switch ?. nature communications, 11: 196. doi:10.1038/s41467-019-13797-9 DOI: https://doi.org/10.1038/s41467-019-13797-9
Guo S, Prentki RJ, Jin K, Chen C, Guo H. (2021) Negative-Capacitance FET With a Cold Source. IEEE Trans. Electron Devices, 68(2): 911-918. doi:10.1109/TED.2020.3041216 DOI: https://doi.org/10.1109/TED.2020.3041216
Salahuddin S, Datta S. (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano letters, 8(2): 405-410. doi:10.1021/nl071804g DOI: https://doi.org/10.1021/nl071804g
Yoon S, Min D, Moon S, Park KS, Won JI, Yoon S. (2020) Improvement in Long-Term and High-Temperature Retention Stability of Ferroelectric Field-Effect Memory Transistors With Metal-Ferrolectric-Metal-Insulator-Semiconductor Gate-Stacks Using Al-Doped HfO2 Thin Films. IEEE Trans. Electron Devices, 67(2): 499-504. doi:10.1109/TED.2019.2961117 DOI: https://doi.org/10.1109/TED.2019.2961117
Mulaosmanovic H, Breyer ET, Mikolajick T, Slesazeck S. (2019) Ferroelectric FETs with 20-nm- Thick HfO2 Layer for Large Memory Window and High Performance. IEEE Trans. Electron Devices, 66(9): 3828-3833. doi:10.1109/TED.2019.2930749 DOI: https://doi.org/10.1109/TED.2019.2930749
Pahwa G, Dutta T, Agarwal A, Chauhan YS, (2018) Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS versus MFIS Structures. IEEE Trans. Electron Devices, 65(3): 867-873. doi:10.1109/TED.2018.2794499 DOI: https://doi.org/10.1109/TED.2018.2794499
Khan AI, Radhakrishna U, Chatterjee K, Salahuddin S, Antoniadis DA. (2016) Negative Capacitance Behavior in a Leaky Ferroelectric. IEEE Trans. Electron Devices, 63(11): 4416-4422. doi:10.1109/TED.2016.2612656 DOI: https://doi.org/10.1109/TED.2016.2612656
Asadi K. (2021) Organic Ferroelectric Materials and Applications. Woodhead Publishing, 1st Edn. DOI: https://doi.org/10.1016/B978-0-12-821551-7.00018-X
Frantti J. (2008) Notes of the Recent Structural Studies on Lead Zirconate Titanate. J. Phys. Chem. B, 112(21): 6521-6535. doi:10.1021/jp711829t DOI: https://doi.org/10.1021/jp711829t
Kim T, Alamo JA, Antoniadis DA. (2020) Dynamics of HfZrO2 Ferroelectric Structures : Experimentals and Models. 2020 IEEE International Electron Devices Meeting (IEDM), 12-18 Dec. 2020, San Francisco, CA, USA. doi:10.1109/IEDM13553.2020.9372013 DOI: https://doi.org/10.1109/IEDM13553.2020.9372013
Saha AK, Gupta SK. (2020) Multi-Domain Negative Capacitance Effects in Metal-Ferroelectric-Insulator-Semiconductor/Metal Stacks: A phase-field Simulation Based Study. Scientific Reports, 10: 10207. doi:10.1038/s41598-020-66313-1 DOI: https://doi.org/10.1038/s41598-020-66313-1
Rahi SB, Tayal S, Upadhyay A K. (2021) A review on emerging negative capacitance field effect transistor for low power electrics. Microelectronics Journal, 116: 105242. doi:10.1016/j.mejo. 2021.105242 DOI: https://doi.org/10.1016/j.mejo.2021.105242
Alam MA, Si M, Ye PD. (2019) A critical review of recent progress on negative capacitance field-effect transistors. Applied Physics Letters, 114: 090401. doi:10.1063/1.5092684 DOI: https://doi.org/10.1063/1.5092684
Tu L, Wang X, Wang J, Meng X, Chu J. (2018) Ferroelectric Negative Capacitance Field Effect Transistor. Advanced Electronic Materials, 4: 1800231. doi:10.1002/aelm.201800231 DOI: https://doi.org/10.1002/aelm.201800231
Pahwa G, Agarwal A, Chauhan YS. (2018) Numerical Investigation of Short-Channel Effects in Negative capacitance MFIS and MFMIS Transistors: Subthreshold Behavior. IEEE Trans. Electron Devices, 65(11): 5130-5136. doi:10.1109/TED.2018.2870519 DOI: https://doi.org/10.1109/TED.2018.2870519
Jain AK, Kumar MJ. (2020) Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study. IEEE Access, 8: 137540-137548. DOI: https://doi.org/10.1109/ACCESS.2020.3012579
doi:10.1109/ACCESS. 2020.3012579
Sreenivasulu B, Vadthiya N. (2021) Design and Deep Insights into Sub-10 nm Spacer Engineering Junctionless FinFET for Nanoscale Application. ECS Journal of Solid State Science and Technology, 10(1): 013008. doi:10.1149/2162-8777/abddd4 DOI: https://doi.org/10.1149/2162-8777/abddd4
Nowbahari A, Roy A, Marchetti L. (2020) Junctionless Transistors: State-of-the-Art. Electronics, 9: 1174. doi:10.3390/electronics9071174 DOI: https://doi.org/10.3390/electronics9071174
Fu Y, Ma L, Duan Z, Han W. (2022) Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor. Journal of Semiconductor, 43: 054101. doi:10.1088/1674-4926/43/5/054101 DOI: https://doi.org/10.1088/1674-4926/43/5/054101
Rassekh A, Sallese J, Jazaeri F, Fathipour M, Ionescu AM. (2020) Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect. J. of Electron Devices Society, 8: 939-947. doi:10.1109/JEDS.2020.3020976 DOI: https://doi.org/10.1109/JEDS.2020.3020976
Reis M. (2013) Fundamentals of Magnetism, ACADEMIC PRESS. doi:10.1016/B978-0-12-405545-2.00011-4 DOI: https://doi.org/10.1016/B978-0-12-405545-2.00011-4
Rassekh A, Jazaeri F, Sallese J. (2022) Nonhysteresis Condition in Negative Capacitance Junctionless FETs. IEEE Trans. Electron Devices, 69(2): 820-826. DOI: https://doi.org/10.1109/TED.2021.3133193
doi:10.1109/TED.2021. 3133193
Awadhiya B, Kondekar PN, Yadav S, Upadhyay P. (2021) Insight into Threshold Voltage and Drain Induced Barrier Lowering in Negative Capacitance Field Effect Transistor. Trans. Electrical and Electronic Materials, 22: 267-273. doi:10.1007/s42341-020-00230-y DOI: https://doi.org/10.1007/s42341-020-00230-y
Rassekh A, Jazaeri F, Fathipour M, Sallese J. (2019) Modeling Interface Charge Trap in Junctionless FETs, Including Temperature Effects. IEEE Trans. Electron Devices, 66(11): 4653-4659. doi:10.1109/TED.2019.2944193 DOI: https://doi.org/10.1109/TED.2019.2944193
Ding Z, Hu G, Gu J, Liu R, Wang L, Tang T. (2011) An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs. Microelectronics Journal, 42: 515-519. doi:10.1016/j.mejo.2010.11.002 DOI: https://doi.org/10.1016/j.mejo.2010.11.002
Jazaeri F, Barbut L, Koukab A, Sallese JM. (2013) Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime. Solid-State Electronics, 82: 103-110. doi:10.1016/j.sse.2013.02.001 DOI: https://doi.org/10.1016/j.sse.2013.02.001
Downloads
Published
How to Cite
Issue
Section
License
Copyright (c) 2022 IIUM Press
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.