Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

  • Zainab Mohamad Ashari
  • Anis Nurashikin Nordin

Abstract

Modern communication and computer systems require rapid (Gbps), efficient  and large bandwidth data transfers. Agressive scaling of digital integrated systems  allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The  Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) and hardware devices. PCIe buses require efficient clock data recovery circuits (CDR) to recover clock signals embedded in data during transmission. This paper describes the theoretical modeling and simulation of a phase-locked loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR circuit is proposed  and elaborated in this work. Simulations were carried out using a Hardware Description Language, Verilog-AMS. The effect of jitter on the proposed design is also simulated and evaluated in this work. It was found that the proposed design is robust against both input and VCO jitter.

ABSTRAK: Sistem komunikasi dan komputer moden memerlukan pemindahan data yang cekap (Gbps), dan bandwidth yang besar. Pengecilan agresif menggunakan teknik sistem digital bersepadu membenarkan bas dan litar pengawal komunikasi disatukan dengan  mikroprocessor dalam cip yang sama. Protokol persisian komponen sambung tara ekspres (PCIe) mengendalikan semua komunikasi antara unit pemprosesan pusat (CPU) dan peranti perkakasan. Bas PCIe memerlukan litar jam pemulihan data (CDR) yang cekap untuk mendapatkan kembali isyarat jam yang tertanam dalam data semasa transmisi. Karya ini menerangkan teori pemodelan dan simulasi gelung fasa terkunci (PLL) untuk CDR. Rekabentuk 5 GHz PLL yang mudah telah dicadangkan dalm kertas kerja ini. Simulasi telah dijalankan menggunakan perisian verilog-AMS. Simulasi mengunnakan kesan ketar dalam reka bentuk yang dicadangkan telah dinilai. Reka bentuk yang dicadangkan terbukti teguh mengatasi ganguan ketar di input dan VCO.

KEY WORDS:  phase-locked loop (PLL); jitter; phase detector; low-pass filter; voltage-controlled oscillator

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Published
2012-01-04
How to Cite
Mohamad Ashari, Z., & Nordin, A. N. (2012). Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR). IIUM Engineering Journal, 12(5). https://doi.org/10.31436/iiumej.v12i5.250

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