EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)

Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor. A comprehensive study of the Negative Capacitance Field Effect Transistor (NCFETis presented. This paper shows the effect of ferroelectric material in MOSFET structure by replacing the insulator in the conventional MOSFET. It should be possible to obtain a steeper subthreshold swing (SS) compared to the one without a ferroelectric material layer, thus breaking the fundamental limit on the operating voltage of MOSFET. 27% of the subthreshold slope reduction is observed by introducing ferroelectric in the dielectric layer compared to the conventional MOSFETs. Hence, the power dissipation in MOSFET can be mitigated and shine to a new technology of a low voltage/low power transistor operation. ABSTRAK: Transistor Kesan Medan Konvensional (FET) terkenal memerlukan sekurangkurangnya 60mV / dekad pada 300K perubahan pada saluran yang berpotensi untuk mengubah arus dengan faktor 10. Oleh kerana itu, 60mV / dekad menjadi hambatan transistor hari ini. Kajian komprehensif mengenai Negative Capacitance Field Effect Transistor (NCFETis dikemukakan. Makalah ini menunjukkan kesan bahan ferroelektrik dalam struktur MOSFET dengan mengganti penebat dalam MOSFET konvensional. Sebaiknya dapatkan swing swing subthreshold (SS) yang lebih curam berbanding dengan satu tanpa lapisan bahan ferroelektrik, sehingga melanggar had asas pada voltan operasi MOSFET. 27% pengurangan cerun subthreshold diperhatikan dengan memperkenalkan ferroelektrik di lapisan dielektrik berbanding dengan MOSFET konvensional. Oleh itu, pelesapan daya dalam MOSFET dapat dikurangkan dan bersinar dengan teknologi baru operasi transistor voltan rendah / kuasa rendah.


INTRODUCTION
Moore's Law drove the scaling trend of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Moore's idea was that the transistor's size would double every 18 months, making the transistor consume less power, become smaller in size, and perform at high speed [1]. Though the downscaling of MOSFET for the past decades continues to grow, it causes another problem to arise, such as short-channel effect, higher power consumption, and gate oxide tunneling effect [2]. https://doi.org /10.31436/iiumej.v22i1.1814 However, researchers have come out with many possible solutions to make sure Moore's Law can be held for the long run. Feedback FET [3], Tunnel FET [4], and Impact-ionization MOSFET [5] are some technologies introduced to hold MOS scaling limits. Yet, Moore's Law is almost reaching its fundamental limit [6]. Therefore, new technologies and physic are needed to cope with the MOS scaling. The voltage scaling of the supply voltage (VDD) almost stopped as a further reduction of the device size, and hence the threshold voltage (VTH) causes the exponential increase in the OFF state current (IOFF). This is a direct consequence of the nonscalability of the subthreshold swing (SS) to below 60 mV/decade. The negative capacitance FET (NCFET) has been proposed by Salahuddin et al. [7][8] as an alternative steep slope transistor to overcome the classical limit of 60mV/dec, and has been extensively studied [8][9][10][11][12][13][14][15][16].
In this paper, the effect of ferroelectric thickness and doping concertation in NCFETS is analyzed to observe the device's performance, which may give further insight for future device consideration.

DEVICE STRUCTURE
The NCFET is designed considering 20nm gate length. Figure 1 and Table 1shows the device structure and its parameters, respectively.
The S/D depths were designed to be shallow (10nm) is to avoid punch-through occurs which typically occurs at lower voltage with a deeper source-drain junction depth. Silicon doped hafnium oxide (Si: HfO2) was used as a ferroelectric material layer due to its superior performance, such as nonvolatility, hysteresis-free, and compatible with complementary metaloxide-semiconductor transistor (CMOS) technology [17]. A buffer layer is used to reduce the gate leakage current and improve the electrical properties of the NCFET [17].  In this paper, five different ferroelectric material layers were used as mentioned in Table  2, various parameters for the thickness are shown. Pseudocode is developed to calculate the parameters of any given thickness of ferroelectric material based on Miller [18]. As the ferroelectric material's thickness increases, the parameters related to the ferroelectric material; remanent polarization, spontaneous polarization, critical electric field, and zero-field relative permittivity decreased. As a result, it can be concluded that the ferroelectric properties are inversely proportional to ferroelectric thickness. This information will help us determine the ferroelectric material parameters when designing a gate structure of MOSFET with the ferroelectric material.

RESULTS AND DISCUSSION
The performance of the NCFETs is observed for different thickness of the ferroelectric thickness, the source-drain doping concentration in I-V characteristics, and subthreshold behavior of the MOSFETs.

Effect of Ferroelectric Layer Thickness on I-V Characteristics ions
Five transistors with different ferroelectric material layer thickness, as mentioned in Table  2, were created using the simulator. All these devices have a buffer layer of 7 Å of HfO2. The simulation on the devices with different ferroelectric material layers is carried out by using Silvaco TCAD to investigate the effect of thickness of the ferroelectric material layer on the I-V characteristics of the devices with 0.5V, 1.0V, and 1.5V gate voltages. Figure 2 shows the I-V characteristics of the devices for various ferroelectric thicknesses. The simulation shows that the saturation slope is decreasing while the current density was increasing. As the thickness increases, the variation of the slope of the drain current increases, and instead of saturation current the behavior of the transistors are moral-less resistive. Figure 3 shows the variation of maximum drain current at VDS = 1.5 V for different gate voltages and the slope at saturation with the ferroelectric thickness variation. It is observed that there is not much increment in drain current for 10nm, 8nm, and 6nm. But as the thickness of ferroelectric material decreased, in this case, 4nm and 2nm, the drain current also increased considerably. For example, for 10nm, 8nm, and 6nm cases, when the gate voltage is bias with 0.5V, there is not much increment. Figure 2 shows that as the thickness of ferroelectric material https://doi.org/10.31436/iiumej.v22i1.1814 decreased, the current increase from 1.55mA to 1.59mA for a 0.5V gate bias voltage. The same case can be seen when the gate bias voltages are 1.0V and 1.5V, the drain current increase from 2.46mA to 2.73mA and from 3.31mA to 3.7mA, respectively. It can be concluded that the thickness of ferroelectric material plays a vital role in the performance of the NCFET.

Effect Of Source Drain Doping Concentration To The I-V
For this simulation, 2nm ferroelectric material thickness is chosen as it gives a higher drain current at lower drain voltage, and source and drain concentration are varying, and the effect of doping concentration on the I-V characteristics are observed and shown in Fig. 4. It is observed that the doping concentration of source-drain increased, the drain current density also increased. However, when the concentration is at 1 x 10 19 cm -3 , there is a high current density observed for 0.5V and 1.0V gate bias voltage, but at a certain point, the current drop and become constant afterward. This effect is said to be a short channel effect due to the results of two-dimensional potential distribution and high electric fields in the channel region. For a given channel doping concentration, as the channel's length is reduced, the depletion layer width of source and drain becomes equal or comparable to the channel length. Failing current saturation due to the punch-through effect [19]. These results show that the doping concentration of source-drain plays a vital role in the performance of the NCFET.

Subthreshold Slope Behavior
For a Field-Effect transistor, the minimum voltage swing needed to turn a transistor from on to off is an important parameter that can be used to define the power dissipated by the device. Drain current with the variation of gate voltage (Id versus Vg) are shown in Fig. 5 for the VDS of 0.05 V, 0.5 V, and 1.0 V, respectively, with different views by scaling up.  The results are tabulated in Table 3, and it is observed that with a lower drain bias voltage, the subthreshold also decrease. This means NCFET can give a steeper subthreshold slope at a lower drain bias voltage.
The input characteristics of the NCFETs and MOSFETs are shown in Fig. 5 in linear and logarithm scale. The NCFETs gives a larger drain current compared to MOSFETs. The NCFET and MOSFET subthreshold slope are 348.37 mV/dec and 446.45 mV/dec for the same device dimensions. The subthreshold slope for the one without ferroelectric material is much higher than the one with the ferroelectric material layer. This shows that, by introducing the ferroelectric material layer to the structure of MOSFET, it is possible to get a steeper subthreshold swing, thus improving the device's performance.

CONCLUSION
In conclusion, a steeper subthreshold slope for NCFET compared to conventional MOSFET has been demonstrated. It is also shown that the performance of NCFET is affected by the thickness of ferroelectric material and source/drain concentration doping. As the thickness of the ferroelectric material layer decreased, a steeper D -DS is observed. While as the source/drain concentration doping increased, a steeper D -DS graph is noticed. It is remarkable that by manipulating the ferroelectric material's thickness and the source/drain doping concentration, the transistor performance can be improved for the NCFET.